Defect-Tolerant Memory With Simple ADDRESS TRANSLATION
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19
This article describes a defect-tolerant memory in which an alter native memory block is assigned an all-binary-ones' address and the output indicative of a match between input and defective block addresses is directly distributed as the all-binary-ones' block address for access of the alternative memory block. This simplifies memory address translation. In the figure, high-order bits (A17-A10) of a memory address (A17- A0) from microprocessor 10 are used as a block address for main memory 14 with low-order bits (A9-A0) used for addressing in the addressed block. Before memory operation, a check is made to determine if the main memory 14 contains a defective memory block.