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Receiver Circuit Disclosure Number: IPCOM000064587D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

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Culican, EF Pritzlaff, P [+details]


Significant reductions in device capacitance are obtained through the use of an improved process lead to circuit speed improvement. Such an improvement, while of advantage to the internal circuits, also acts to reduce the receiver speed and is accompanied by an undesired decrease in AC noise tolerance (which is directly related to how fast a pulse edge will propagate through the receiver). The disclosed circuit design change incorporates several resistors and a capacitor (TDC) to control the positive-negative transitions as well as the AC noise input of a given receiver. Fig. 1 discloses a circuit design which slows down the receiver. The 15K resistors tend to slow down the pulse edge which rises at the input (falling at the output). The 25K resistor slows down the other edge.