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Data Scrambler/Descrambler With Look-Ahead

IP.com Disclosure Number: IPCOM000064610D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Boerstler, DW [+details]

Abstract

In a serial data transmission system in which a binary 1 (for example) is represented by a transition on a signal-carrying line and a binary 0 is represented by the absence of a transition, a linear feedback shift register is connected to receive the original serial data and to translate it into a pattern that does not contain a sequence of 1 bits greater than a predetermined length. A binary counter is connected to receive the modulo two sum of the outputs of several stages of the register. The connection of the counter to the register stages is arranged so that the value in the counter equals the number of consecutive 1 bits that will later appear in sequence at the output of the shift register. When the count reaches the predetermined number, a 0 bit is inserted into the output and the sequence of 1 bits is terminated.