Short Pulse Selective Latch Memory Decoder
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19
A method for allowing short duration true/complement (T/C) address pulses to perform a decoding function for a serial secondary port on a DRAM (dynamic random-access memory) chip is featured. Two address lines (4 binary combinations) are fed into four unique decoders, one of which is illustrated. When address lines A1 or A1 and A2 or A2 are pulsed and fed to the decoders (transistors 8 and 9), all four decoders will be activated but three of the four will fail to have a valid decode and drop out. The only valid decoder will be latched up to enable a drive pulse (0 to drive a DRAM chip decode /DR) function. (Image Omitted) At the beginning of the cycle, node A of the latch (transistors 1 - 4) is low and node B is high.