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D-Type Latch in Cascoded Emitter-Coupled Logic

IP.com Disclosure Number: IPCOM000064653D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

This article describes the design of a single cell, ECL (emitter- coupled logic) I/O compatible latch circuit. D-type latch circuits have been implemented previously within one logic cell in TTL (transistor transistor logic) gate arrays; however, the latch input/output levels are not TTL compatible nor conveniently implemented for more than one input port. This problem is solved by the use of the simple CECL (cascoded emitter-coupled logic) shown above. The two-level single rail CECL latch circuit here disclosed is ECL compatible and allows for easy addition of input ports. Level 1 (L1) is the master latch (Fig. 1) with two input ports and latch 2 (L2) is the slave latch (Fig. 2), with A clock on C2, SCAN IN on D2, C clock on C1, DATA IN on D1, B clock on C, L1 on D and L2 SCAN OUT.