Improved Parity Checking
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19
On VLSI chips with a large number of logic gates and embedded storage arrays, data can be checked in the logic part by using two rails for each bit, whose polarity must be complementary [*]. However, this checking method by complementary switching is unsuitable for storage arrays, for which purpose a parity bit would have to be generated before data are fed to the storage array. The time needed for parity bit generation would intolerably increase the access time. The method described in this article uses a separate storage for storing the parity bits. This separate parity storage can be kept very small and the access time very short. As shown in Fig.