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Bit Line Restore Circuit for High-Speed CMOS Arrays

IP.com Disclosure Number: IPCOM000064672D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Haug, W Helwig, K Loehlein, WD [+details]

Abstract

The illustrated fast bit line restore circuit for CMOS arrays consists of a biasing generator (BG) with transistors T8 and T9 as well as decoupling capacitor CD and restore field-effect transistors T21 and T22. In the non-addressed state, the restore circuit for bit lines BLT and BLC permits raising their potential to VH - VT by means of restore pulse R shown in the time diagram. If the static 6-device storage cell, consisting of transistors T1 to T6, is selected by word line WL and bit switch line BS, the potential of bit line BLT, for example, drops from VH - VT to VH - VT - WV. After WV = 0.5 V has been reached, set sense latch line SL switches to up level, and the potential of true data bus DBT rapidly drops to 0 V. The upper part of the circuit diagram shows the biasing generator generating the DC voltage VB = VH - VT.