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Testability Improvement in Embedded Array READ Circuit Disclosure Number: IPCOM000064674D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

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Fields, DB Heitmueller, WR [+details]


Disclosed is a circuit arrangement that permits the testing of the embedded array READ circuits (Fig. 1) for some AC characteristics by using only DC test methods. The physical relocation of the sense resistors on the first level metallurgy land patterns permits the testing of the land patterns for discontinuities. As illustrated in Fig. 2, the disclosed technique for accomplishing some AC testability is accomplished by physically locating the load resistors R1 and R2 of the read circuit of Fig. 1 at the remote end of the bit lines. This configuration does not create any changes in the circuit function or parameters but simply permits more of the first level metallurgy to be tested for opens using simple DC test methods.