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Write Improvement Method for Schottky-Coupled-Type Cell

IP.com Disclosure Number: IPCOM000064689D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Eardley, DB Wang, W [+details]

Abstract

This disclosure applies a polysilicon resistor in the emitter section of a Schottky-coupled-type cell or a complementary transistor switching (CTS) cell to improve the write performance of the cell. In a contemporary circuit configuration, during the write operation of a Schottky- coupled-type cell, part of the current (Iw) is lost to the cell's word bottom line via the "on" NPN. This phenomenon reduces the amount of current available to charge up the rising bit line (BL) and results in extended write delays (Tw) for these types of cells. The addition of a polysilicon resistor in the emitter (Figs. 1A and 1B) reduces the inherent write delay associated with these cells without increasing the bit line write currents.