Voltage Regulator Circuit for Cmos Substrate Voltage Generator
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19
This circuit regulates the substrate voltage VSX to -3.0 + 10% volts. Without it, the voltage VSX could exceed -7.0 volts, seriously degrading chip performance. The improved regulation is achieved by application of voltage division between VDD and VSX rather than VSX and ground. In normal operation of the regulator circuit, transistor T4 is biased "on", pulling OUT low, thus enabling the substrate generator. T1 and T2 are ratioed such that as VSX approaches -3.0 V, T4 begins to turn off allowing OUT to rise and disable the VSX pump. Tying the gate of T2 to VSX causes VGS(T2) to be approximately equal to VGS(T1). Transistor T4 is made long enough to reduce sensitivity to process variations which might otherwise cause serious fractional variations in length.