Browse Prior Art Database

Data/Test-Controlled Memory Architecture for Supercomputers

IP.com Disclosure Number: IPCOM000064701D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Chang, RW Troutman, BC [+details]

Abstract

In a conventional computer memory, the selection and modification of memory index registers is controlled only by instructions. Such an architecture works well for a conventional computer, but is inefficient for a supercomputer that contains many processors and memory units, particularly when the operations involve decision-making processes. An architecture, EXTEN, shown in Fig.