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CMOS Self-Decoding Complementary Pass Gate Multiplexer Disclosure Number: IPCOM000064704D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

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Ogilvie, CR Shepard, KR [+details]


This complementary metal-oxide semiconductor (CMOS) circuit utilizes a combination of P and N channel devices to build complementary pairs into a binary tree which is implemented as a self-decoding pass gate multiplexer. The self-decoding complementary pass gate multiplexer shown in Fig. 1 multiplexes the data lines (D0-D7) as well as decodes the address lines (A,B and C) in one circuit. The most primitive form of a CMOS multiplexer is shown in Fig. 2 and is the basic building block for any number of data inputs while still requiring only enough control lines to address the data field. The circuit operation in Fig.2 is as follows: If address line A is 0 volts, the P device turns on and the data line D0 is selected. Likewise, if line A is at plus 4.