Multiple Clock Frequency Generation
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19
This disclosure describes a circuit for generating single- and double- frequency clock pulses by utilizing only the leading edge of an oscillator pulse for both clock signals, without dependence on the oscillator pulse width. As shown in the figure, oscillator pulses supplied to input 10 are inverted by inverter 11, whose output is connected to inverter 12 and one input of NOR gate 13. The output of inverter 11 is also connected to output 14 which supplies the single-frequency clock signal F1. The output of inverter 12 is connected through delay 15 to the other input of NOR 13. The non-inverted output of NOR 13 is connected to inverter 16, whose output is connected through delay 17 to one input of OR gate 18.