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IBM Series/1 Status Level Improvements to Provide Rapid Changes of Interrupt Levels

IP.com Disclosure Number: IPCOM000064723D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Ho Lung, MG Mansfield, S Thatcher, LE Villante, AE [+details]

Abstract

A technique is described whereby improvements are made in the IBM Series/1 Status Register microcode, so as to provide a rapid means of changing from one interrupt level request to another. The IBM Series/1 requires four priority interrupt levels, each with its own Level Status Register (LSR), which resides in local memory. To store a level LSR, microcode now simply requires the ability to source the Hardware Level Status Registers (HLSR) and then store it in the appropriate priority level LSR. The improvement described herein uses only one sixteen-bit status (ST) register, whereby microcode is used to implement the SR so that it functions as two separate registers, ST and HLSR, each having its own destination and next source decode.