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Threshold Voltage Shift Avoidance During Plasma Etching of Insulating Films in Construction of FET Devices

IP.com Disclosure Number: IPCOM000064724D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Hechmer, PA Kim, SU Lundell, SO Puttlitz, AF Strong, JE [+details]

Abstract

By inserting a thick (1/16-inch) quartz plate (backer) between wafers being etched and the anode of a parallel plate RF etching system (Fig. 1), the voltage developed internal to devices on the wafers is reduced sufficiently such that the threshold voltage (VT) shift previously experienced is no longer a yield detractor. When silicon nitride was etched in a parallel plate etcher, threshold shifts of -3 volts and resultant device yields of less than 50% were not uncommon in a particular field-effect transistor (FET) product having unprotected gates. Wide variation of VT shift per se was experienced within wafers and from wafer to wafer. Moreover, wide variation in the magnitude of VT shift was found between tools. In contrast, VT of devices with their gates tied to diffusions or protect diodes did not shift.