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Lateral PNP Memory Cell With Current Source NPN Loads

IP.com Disclosure Number: IPCOM000064767D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Cavaliere, JR Eardley, DB [+details]

Abstract

The static memory cell circuit is comprised of lateral PNP flip-flop connected transistors T1 and T2 and NPN loads T5 and T6 and is emitter coupled (T3 and T4) to the bit lines. The circuit is capable of a high ratio of "read" to "standby" current and requires only two isolated subcollectors per cell. The operation is described with exemplary parameter values. READ OPERATIONS During the "read" cycle, lines Yl and Y2 are at +2.7 V. Line Wl is initially at +2.3 V. Lines W2 and W3 are at +1.35 V and +0.7 V, respectively, causing T5 and T6 collector currents to be 1.4 mA each. Assume that T1 is "on". T1 collector current is 2.8 mA. Schottky diode D1 is forward biased and conducts 1.4 mA. The collectors of T1 and T2 are at +2.17 V and +1.70 V respectively. T2 is "off" and D2 is reverse biased.