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Low Threshold Stacked CMOS Devices Utilizing Self-Aligned Silicide Technology

IP.com Disclosure Number: IPCOM000064770D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Balasubramanyam, K Hanafi, H [+details]

Abstract

A salicide (self-aligned silicide) is used to lower work function in the P-channel devices, thus lowering their threshold voltage (VT) from the -3 to -4-volt range to the -1.5 to -2-volt range. A 5-volt power supply becomes possible rather than the 10 to 20-volt supply previously required to obtain functional circuits. SCMOS (stacked complementary metal-oxide silicon) structures compatible with N-channel metal-oxide silicon (NMOS) technology have been proposed [*]. The P-channel device is made from laser-annealed polycrystalline silicon and is superimposed upon the N-channel device. The single Poly I gate is common to both devices. P-channel threshold voltages of about -3 to -7 volts are obtained using this technique.