Browse Prior Art Database

Trinary Trigger

IP.com Disclosure Number: IPCOM000064785D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Thompson, RE [+details]

Abstract

A trinary trigger is a simple means to provide a sequenced three-phase output for use in general-purpose logic functions. The present embodiment requires fewer circuit elements than other known trinary triggers, and is not dependent on internal delays of individual circuit elements. Fig. 1 shows that the trinary trigger logic is embodied in nine NOR circuits with two inputs, reset and clock, and three outputs. Fig. 2 shows the timing of polarity transitions of the input and NOR output lines as the circuit function proceeds. In all cases the high level (up) equals plus, and the low level (down) equals minus. Referring to Fig. 1, it is seen that RESET line 100 provides input to NOR circuits 30, 40, 50, 80, and 90. It is seen that, therefore, when line 100 is plus, NOR OUTPUT lines 31, 41, 51, 81, and 91 are held negative.