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Role of Simulation in Partial Array Usage Audit

IP.com Disclosure Number: IPCOM000064786D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Pruden, DW Sweet, CP [+details]

Abstract

A simulator is used to audit pins on embedded arrays to determine if circuit connections to the pins meet technology requirements. These requirements specify whether a non-isolated device pin must be tied 0, tied 1, tied 0 or 1, or must not be tied. A MASK value and a RESULT value are defined for all possible pin requirements in the chart. For example, if a pin is required to be tied 1, the MASK value is 0 and the RESULT value is 1. The verification process is as follows: 1. For each (non-isolated) pin on the array, determine its MASK and RESULT value. 2. Have the simulator reset the circuit to U and propagate any values from tie blocks using the four valued simulation tables. After this simulation, pins not tied have a value of U, pins tied 0 are at a value of 0, and pins tied 1 are at 1.