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(p,q) COUNTER IN DIFFERENTIAL CECL

IP.com Disclosure Number: IPCOM000064789D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

A (p,q) counter encodes the number of "1" bits among p bits, into q bits in binary representation. (p,q) counters are useful in ALU designs and have been investigated by many people. A cascode emitter- coupled logic (CECL) implementation is disclosed herein along with algorithms. The algorithms conceived for this design can be illustrated with a (7,3) counter, as represented in Fig. 1. (X6, X5 .... x0) are input bits. (R2, R1, R0) are output bits Each row of bits is obtained as follows: a0 = X0 Ai = X0 v Ai-1 For i = 1 ...6 Yi = Xi . Ai-1 (b2), (Zi), (Ci) are obtained in the same manner. If these logic functions are performed sequentially with X0, X1 one bit at a time, this algorithm essentially describes the action of a conventional binary counter.