Browse Prior Art Database

Hardware Reset of LSSD Logic Chip During System Operation (Programmable Reset)

IP.com Disclosure Number: IPCOM000064790D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Alana, MG Clayton, ST [+details]

Abstract

A logic patch is used to reset latches that were not reset at the end of the previous operation in a level sensitive scan design (LSSD) logic chip. Because any latch in an LSSD designed logic is accessible through its scan string, it is possible to reset that latch or reconfigure the state of any LSSD module to correct an extremely complex patch for logic problems in the logic design. The module scan of LSSD logic chips, during system operation, to reset or reconfigure latches is accomplished in the following design. A latch 1 is set, capturing a signal, indicating that an ending state has been reached. This immediately forces "SCANMODE" 2 to become active. An erasable programmable read-only memory (EPROM) 3 contains the bit pattern for the shift register latch (SRL) scan string of the chip to reset.