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Cross-Coupled FET Exclusive-Or/Compare Circuit

IP.com Disclosure Number: IPCOM000064837D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Case, JR [+details]

Abstract

A conventional FET exclusive-OR (EOR) circuit has several disadvantages. Thus, it is not symmetrical in the two inputs, and it is physically large and relatively slow. In addition, it is cumbersome in making N-way compare circuits. A circuit is described which offers substantial improvement over the conventional EOR circuit. This EOR/compare circuit consists of two cross-coupled FET switch devices with a load device, as shown in Fig. 1. As can be seen, the circuit is symmetric in the two inputs A and B. Additional advantages of this circuit are that the circuit is physically smaller, is faster, and has lower power consumption than a conventional exclusive-OR. The extension of this circuit to an N-way compare is straightforward, as can be seen in Fig. 2. The logical expression for the Fig.