Behavioral Fault Simulation
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19
An algorithm is described for doing behavioral (functional) level fault simulation. In the past, the only tool for determining the completeness with which a set of test vectors could detect manufacturing defects in integrated circuits has been to use gate level fault simulation. With the drastic increase in the size of these chips, the computing resources required to accomplish these simulations are putting a strain on computing capabilities. An algorithm for propagating faults through high level behavioral models greatly reduces these resource requirements. Further, if designs use complex off the shelf parts developed by third party manufacturers and the detailed gate level design is totally unknown, it is impossible to perform gate level fault simulation.