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Gated Word Current Switch Circuit for Bipolar RAM Disclosure Number: IPCOM000064849D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

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Chan, YH Homa, WS Struk, JR [+details]


Bipolar random-access memories (RAMs) using complementary transistor switch (CTS) cells [*] are sensitive to address noise. To overcome address noise problems, two solutions exist: (1) well-controlled system address timing, and (2) on-chip address gating. This article describes the design of the second approach. In a gated address design, a system address clock is used to control the word and/or bit address paths within a chip. The word and/or bit selection can be gated off when the chip is inactive, so that address changes will have no effects on the array cells. Fig. 1 presents a circuit means to perform address gating on the word path for a chip with a current-mode word line selection scheme. Circuit Description For the purpose of illustration, an array with 128 word lines by 80 cells is considered in Fig. 1.