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Generalized Scan Test Technique for Vlsi Circuits

IP.com Disclosure Number: IPCOM000064850D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Debord, P Glaise, R [+details]

Abstract

A serious problem in designing with LSI (large-scale integration) is the inaccessibility of internal signals. Past techniques tested the LSI chips with complex sequential patterns with which the internal circuits were put through all their paces while the results were transferred to the output pins of the chip for observation. Given present chip complexity, this process takes too long and is thus inefficient. The LSSD (level sensitive scan design) technique has been developed to enable every LSI chip to be completely tested for DC faults with the aid of computer-generated test data. With LSSD, the shift register latch is the only type of storage element, other than RAM chips, permitted in a logic design.