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Optimization of a Delay Line Application

IP.com Disclosure Number: IPCOM000064852D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Dillon, GE [+details]

Abstract

Tape storage control unit architecture requires a circuit which provides two clock pulses when a specific line is activated. The timing relationships for these pulses are shown in Fig. 1. When the tag line becomes active, clock pulse C1 becomes active approximately 't' time later and remains active for 50 nsec. When C1 becomes inactive, 50 nsec later C2 becomes active and remains in the active state for 50 nsec. The 't' time is specified as being the minimum amount of time between the TAG and the first clock pulse. The circuit shown in Fig. 2 to produce these pulses includes one positive edge-triggered D-type latch, one 150-nanosecond delay line, and a small amount of combinational logic. After a reset condition, the latch and the delay line are at state '0'.