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Fully Testable Lssd CLOCK Generator Circuit

IP.com Disclosure Number: IPCOM000064855D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Iverson, JH Reetz, DD Sutheimer, KA [+details]

Abstract

The above circuit generates non-overlapping clock pulses from a single oscillator. By using additional logic for test control, it is possible to completely test logic blocks in the circuit for a stuck-fault condition. A stuck-fault condition, as applied to either an input or output of a circuit, is considered tested if it creates a detectable difference at the output of the circuit. In normal operation, the oscillator signal A is applied simultaneously to OR 8 and inverter 12. Circuit 8 ORs the oscillator input A with test input Al, and circuit 10 NANDs that result with test input A2. In normal operation, A2 would be up and Al would be down so that both NAND 10 and inverter 12 invert input A. The output of NAND 10 is again inverted by inverter 14 and applied to AND 16.