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Double Port RAM in CMOS Technology Disclosure Number: IPCOM000064856D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

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Nuez, JP Piccino, C [+details]


Shown in the drawing is a memory cell which has a low gain during write operations and which can be used in a double port random-access memory (RAM) in complementary metal-oxide semiconductor (CMOS) technology. The bistable memory cell comprises transistors T1, T2, T3 and T4 whose V+ power supply is provided through transistor inverter arrangement T7 and T8. This transistor inverter is switched by a signal on the WRITE WORD line. The cell is accessed through transistor T5 and bit line port 1 and by transistor T6 and bit line port 2. During a write operation, the WRITE WORD control line is switched to an UP level. Thus node C is grounded, and the write operation is performed without any difficulty as the cell is unpowered. Only one bit line is used for writing purposes.