Pseudo-Clock Driver Identification on Array Chips
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19
This article concerns a means for eliminating false race-like conditions on array chips during validation of RITs (Release Information Tapes) used in an Engineering Design System (EDS) having arrays with latched outputs. A false race indication can occur when a 10-X simulation is performed on a multi-chip module and can hide the presence of a "true" race. This necessitates a time-consuming reprocessing of the multi-chip module at a lower X simulation and may lead to a potential failure at final test due to race conditions. The disclosed solution to this problem involves the identification and insertion of a psuedo-clock driver during validation of the RITs having arrays with latched outputs. The clock driver identification process used for logic chips [*] is determined by clock driver BTRs (block transformation rules).