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Valid Output Indicator of Multi-Port Arrays Disclosure Number: IPCOM000064891D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

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Daghir, KS Shen, M [+details]


When multi-port arrays are self-tested, the following problems exist: 1) the occurrence of simultaneous 'write' and 'read' from two or more ports into the same address during the same cycle, e.g., an indeterminate state, and 2) the contention arising between two or more ports trying to simultaneously 'write into' and 'read from' the same address, during the same cycle, resulting in potentially invalid data. It should be noted that simultaneous 'reading' from two or more 'read' ports from the same address poses no problem since 'read address selection' is not supposed to change the stored data. These two problems are resolved as follows. Fig. 1 shows a circuit schematic of an on-chip comparator or 'multi-exclusive OR' designed for self-test. Its output is a logical 'zero' only if two ports try to select the same address.