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Optimizing Physical Cable Lengths and Access Time of a Bsm

IP.com Disclosure Number: IPCOM000064905D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Albaneze, PR [+details]

Abstract

This arrangement solves the problem of providing the same length cables, on the fetch and store data busses, to each array card or sets of array cards. Also, the control card functions are assigned such that fetch access time is optimized. The cables enter the Processor Memory Array (PMA) at the upper left as shown in Fig. 1. The cables plug into socket positions Y and Z. Board wiring routes the signals to the array cards and control cards. The PMA uses 2 control cards located at postions B and W and 18 array cards located at positions C through V. The commands that the Processor Memory Control (PMC) can issue to the PMA are: Fetch Transfer . Under a fetch transfer up to 16 doublewords (DWs) may be transferred from the PMA to the PMC. Each DW is transferred in 1 machine cycle namely, 18 ns. Store Transfer .