Self-Test/Connection Technique for Wafer Scale Integration Memory
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19
A method is described in this publication whereby a wafer scale integration (WSI) memory can be autotested and configured. This self- test and connection technique for WSI potentially significantly lowers the cost of the final product and consequently makes WSI for memory more attractive. A memory self-test technique exists in the prior art whereby test pattern generator circuits are placed on the wafer either in the kerf or at special chip locations. Additionally, signature collection and compression circuits have been described as one example of verifying correct operation. Based on the aforesaid techniques, the following technique is described for WSI memory. Configure the memory WSI wafer with appropriate memory chips with suitable capacity (e.g., 1k x 1 or 4k or 64k etc.).