Penalty-Free Mechanism for Address Generator Interlock Avoidance
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19
A method of improving high-end processor performance by providing a penalty-free mechanism for address generator interlock (AGI) avoidance. In a processor design it is important that mechanisms which are employed to anticipate future action are penalty-free when wrong. Unfortunately, in a resource constrained environment this is often not the case and an erroneous putative action can create a larger than usual delay. An example of this is the unnecessary use of cache bandwidth which is diverted from necessary instruction fetching. Using these putative actions is then undertaken only on balance. Additional resources, such as cache bandwidth, often reduce the wrong guess penalty and make putative approaches more practical.