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Integrated Cascode Circuits Disclosure Number: IPCOM000064925D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

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Swietek, DJ Wong, RC [+details]


Multiple stages of logic can be combined into a single stage of cascode logic circuitry although a relatively large silicon circuit area is required because of the additional wirings and devices. The technique here disclosed reduces both wiring and device area requirements of such a combination by integrating transistors at adjacent cascode levels, operating the upper level transistors in inverted mode and the lower level transistors in normal mode. A two-level, single-ended CECL (cascode emitter-coupled logic) gate is used by way of example in the figures. The conventional exclusive-OR (XOR) gate is shown in Fig. 1, and the integrated version of the gate in Fig. 2.