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Gated Cmos PLA and Array Load

IP.com Disclosure Number: IPCOM000064933D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Dewanz, DM [+details]

Abstract

This circuit prevents the accidental discharge of a precharged PLA (programmable logic array) product term through coupling into the OR array. The circuit is active only when the OR array is being accessed, thus minimizing the impact of the circuit on the AND array delay. To begin the cycle, both the AND clock and the OR clock drop. This turns on field-effect transistor devices 2 and 6, pulling up the product term, node b (and node a as well) to VDD. This turns off devices 1 and 5, and turns on device 4. When the AND clock rises, device 6 turns off and the AND array is evaluated. If the product term is not selected, it will discharge to ground. This turns on device l, and shuts off device 4. After the slowest product term has discharged, the OR clock rises, shutting off device 2 and turning on device 3.