Browse Prior Art Database

Clock-Chopper Testability

IP.com Disclosure Number: IPCOM000064948D
Original Publication Date: 1985-Sep-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
DeFazio, JJ [+details]

Abstract

This article addresses the testability of a clock-chopper circuit under chip pin-limited conditions. A clock-chopper is a circuit that generates an output pulse whose width is less than that of the input pulse. For consistency of implementation, allowing for a fully stuck-fault testable design, the design rules require that the output of the clock- chopper be tied to a primary output pin to insure that it is fully tested. The disclosed clock-chopper circuit design saves an I/O pin, thereby satisfying this requirement where a chip is pin-limited. Fig. 1 shows a typical clock-chopper implementation using OR/NOR logic. The Data and Test SRLs (shift register latch circuits) have been added as part of the disclosed scheme for testing stuck-faults. Fig.