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Voter Frequency Control Loop for Global Common CLOCK

IP.com Disclosure Number: IPCOM000065002D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Bailey, JA Dimitri, KE [+details]

Abstract

This circuit digitally controls the frequency of a global common clock, without the need of complex analog signal processing and without a digital-to-analog converter. The circuit uses digital logic for averaging and computing a resultant error signal from a multiple parallel signal pulse processor. The error signal adjusts and controls the frequency of the global common clock with respect to its previous resultant frequency, using the configuration shown in Fig. 1. The digital voter computes the sum of each individual signal vote by using the circuit shown in Fig. 2. Each signal vote is first synchronized to BIT CLOCK using D latches. The early and late votes are summed separately. Each sum is used as the address or select input for an M-to-1 multiplexer. The data inputs consist of clocks Q1 through QM .