Browse Prior Art Database

Low Power Memory Cell

IP.com Disclosure Number: IPCOM000065003D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Culican, EF Eaton, PL Pritzlaff, PE [+details]

Abstract

As chips become larger and contain more circuits, the need to mix logic and array on the same masterslice increases. The disclosed cell may be used on a logic masterslice. It operates over a wide range of power supplies and like a logic masterslice does not require AC testing. Since this circuit operates over a range of supplies, the supplies can be lowered to offer a lower circuit power. This supply versatility can also be used to widen the supply tolerances, making the system design easier. The DC testability is important because the user can vary the array organization without requiring a new masterslice for test purposes. The write mechanism is clearly seen when one considers that T1 and T4 create a particular state for a given write pulse and data. With the data line low a write pulse forces node C2 low.