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Memory Interleave With Minimum Signal Lines

IP.com Disclosure Number: IPCOM000065030D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Beacom, TJ Krolak, DJ Weller, GK [+details]

Abstract

Memory interleaving shortens the effective memory access and cycle times. In the past, interleaving required multiple copies of address and/or data busses, to prevent interaction between different partitions of memory. That greatly increased the amount of wires necessary to implement interleaving. A method of interleaving is described which keeps the interface lines to a minimum. In fact, no more interface lines are necessary between a memory controller and the memory than if interleave was not implemented. A block diagram of two memory array cards 10 and 12 and a controller 14 is shown in Fig. 1. A common address bus 16, a common data bus 18, and two unique select lines 20 and 22 couple the controller 14 to the two array cards 10 and 12.