Browse Prior Art Database

Voice/Data Multiplexing in a Multi-Signal Processor-Synchronized Architecture

IP.com Disclosure Number: IPCOM000065033D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Blanc, A Jeanniot, P Spalmacin-Roma, S [+details]

Abstract

The purpose of the proposed mechanism is to concentrate coded voice and data on the same high speed SDLC (Synchronous Data Link Control) aggregate link. The digital output for each signal processor (SP) after running the concentration algorithm is N KBps including overhead. A voice activity detector (VAD) allows the non-transmission of the voice packets corresponding to the silence. The silence is artificially regenerated at the other end. During a conversation, the VAD detects silence during about 50% of the time. If we assume that the high speed link is a V KBps link (V = N x p), and if we assume that the maximum activity of each voice connection is e Erlang (e