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Nonvolatile RAM Failure Rate Reduction Through the Use of Redundancy and Error-Correction Code

IP.com Disclosure Number: IPCOM000065074D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Carlson, BA Verdoorn, WG [+details]

Abstract

Through the use of columnar data redundancy, error-correction code (ECC), and an algorithm that allows recovery from both data and address I/O stuck faults, the effective failure rate of a 256x4-bit nonvolatile random-access memory (NVRAM) can be reduced considerably. An NVRAM is composed of two memory arrays placed in parallel. One array is composed of static RAM cells, and the other array of EPROM cells. The EPROM cells are used in save/restore operations, while the static RAM portion of memory is used for normal memory accesses. To achieve the desired failure rate reduction of the NVRAM, data is stored by columns in alternating directions (Fig. 1). Four copies of data with ECC are stored in the NVRAM, one copy per column. This allows recovery from any data I/O failure.