Browse Prior Art Database

AGEN Within the CACHE

IP.com Disclosure Number: IPCOM000065084D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Emma, PG Pomerene, JH Rechtschaffen, R Sparacio, FJ [+details]

Abstract

A method of eliminating address generate interlock (AGI) within certain designs is described. In most conventional IBM System/370 processors the address generation (AGEN) occurs within the processor instruction element because the component parts which are added together (base/index/displacement) are available therein. If the general-purpose register (GPR) contents are being brought in from the cache, an AGI occurs and in certain designs the lost cycle of AGI can be eliminated by performing the AGEN with the cache AGEN. CACHE. To simplify the explanation, assume a design with a separate DECODE and AGEN cycle and a true one-cycle cache. That is the time between the end of AGEN and the return of the operand is 1 machine cycle.