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Refresh Test of Dynamic Ram

IP.com Disclosure Number: IPCOM000065088D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Guttmann, JE Olson, DR [+details]

Abstract

In the past, refresh of dynamic random-access memory (DRAM) was tested by writing data to memory and waiting for a period of time before reading back the data. If the refresh operation was not occurring, the data stored would decay and result in bad data being read. This invention tests the DRAM refresh operation by monitoring the DRAM -RAS (active low row address strobe) signal, eliminating the need for a long waiting period during the test. The DRAM -RAS signal is active under two conditions: (1) when the DRAM is accessed for a read or write operation, and (2) when a refresh cycle takes place. Because of the periodic nature of DRAM refresh, if no read or write access cycles are taking place, the -RAS signal will appear as a periodic pulse train.