Zero Defect Word Line Test
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19
The proposed test allows screening word line (WL) defects in VLSI memory arrays with static cells having high data retention characteristics. Typical modern storage cells with long data retention are of the MTL/I2L type, as described, for example, in the IBM Technical Disclosure Bulletin 21, 231-232 (June 1978). For reasons of processing yield, a complete memory chip with an array of such cells (e.g., 128 WLs and 160 bit lines (BLs) in 10 channels) frequently comprises a redundant data channel (9/10 good). Defective storage cells are thus allowed. It may happen, however, that an interlevel short (ILS) occurs between a word line (first metal layer) and a bit line (second metal layer).