Browse Prior Art Database

High Speed FIFO Queue for Video Applications

IP.com Disclosure Number: IPCOM000065112D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Mansfield, RL Pettit, PO Romero, HG St Clair, JC [+details]

Abstract

In an all-points-addressable (APA) display adapter, the screen memory must be able to support two separate types of accesses: from the system to modify the display and from the video interface to refresh the screen. In high performance systems, this dual-access situation leads to the use of memories with very high bandwidths, and this can be achieved by using "Page Mode" or "Nibble Mode" capabilities of dynamic RAMs (random-access memories). A problem arises when data is read in bursts from the memory but needs to be provided in a continuous stream to the monitor. This problem is solved using an integrated circuit on the interface between the screen memory and the video path to the monitor. A FIFO (first-in, first-out) queue is used within this integrated circuit.