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Circuit for Updating Bit Map-Memory of a Display Adapter

IP.com Disclosure Number: IPCOM000065118D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Bohrer, K Mansfield, R Pettit, P Romero, H St Clair, J Wagoner, J [+details]

Abstract

All-points-addressable (APA) display adapters allow software to control each pel (picture element) on a monitor. This flexibility to control each pel requires managing a large number of elements. The integrated circuit shown in Fig. 1 handles this bit manipulation in the screen memory. As shown in Fig. 1, the circuit comprises system registers S1 and S2, mask registers M1 and M2, RAM (random-access memory) input registers D1, D2 and D3, barrel shifter (BS), logic unit (LU), and foreground-background color control (FB-CC) shown also in detail in Fig. 2. The system registers S1 and S2 are the means by which the system can write data directly to the RAMs. This data is combined logically with the data being held in the data mask registers M1 and M2, and then passes to the logic unit LU.