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Write Time Improvement of Bipolar Cells

IP.com Disclosure Number: IPCOM000065119D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Hsieh, CM Srinivasan, GR [+details]

Abstract

Bipolar array chips using cells without Schottky barrier diode clamps are slow in consecutive write time because of npn transistor saturation. The following method reduces the transistor beta and reduces the diffusion capacitance in order to cut down the storage time and speed up the write time. In the array area alone, thickness is reduced by selective etching. By using a block-out mask, the periphery of the chip is blocked out and only the array area is exposed to etching, as shown in Fig. 1. The epi thinning in this area can be accomplished by reactive ion etching (RIE) or wet etching directly, or by oxidizing and etching technique.