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Programmable Logic Sequencer for High and Low Speed Events

IP.com Disclosure Number: IPCOM000065128D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Riley, MW [+details]

Abstract

An arrangement is described to permit one Programmable Logic Sequencer (PLS) to be used to generate high speed and low speed events in a logic design. This approach reduces potential cost and amount of board space used by a two-sequencer solution. Control logic that requires generation of signals for both low speed and high speed events can be designed quickly when using PLS. The obvious solution for designs requiring low speed and high speed events would be to use two PLSs. One sequencer would handle low speed events, and the other would handle high speed events. This solution increases the cost and board space used by the design. For a single PLS solution, the sequencer must be clocked at a high rate to handle the high speed signals and the sequencer must also be capable of handling the low speed signals.