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Emulation of Bus Control Strobes for IBM PC and PC/AT Disclosure Number: IPCOM000065130D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

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Riley, MW [+details]


A low cost hardware emulator of the IBM Personal Computer (PC) and the IBM Personal Computer model PC/AT bus control strobes is shown in Fig. 1. It is designed to dynamically switch between two modes of operation using a Programmable Logic Sequencer (PLS) 10, a Programmable Array Logic (PAL) device 11, and a shift register 13 as the basic control for systems which are not provided with an INTEL microprocessor type 8088 or 80286. The basic hardware required for the control signal generation is a PLS 10, a PAL device 11, and a shift register 13. This logic is assisted by additional logic 14 and qualification logic 15. The function of PLS 10 in this design is to generate all the major control timing signals to the supporting logic. The shift register 13 is used to synchronize control signals to the +4.