Browse Prior Art Database

Programmable Logic Array

IP.com Disclosure Number: IPCOM000065135D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Gurule, E Pisciotta, C [+details]

Abstract

In certain types of group code recording, data is taken from the channel at a different rate than it is written out to tape (seven bytes are taken in at the same time ten bytes are shifted out). Since both functions must be monitored and controlled (or counted), the programmable logic array (PLA) must be clocked at two different frequencies. A channel rate clock is needed so that the PLA can count channel data bytes for resync purposes, etc. A write clock is needed to insert the correct number of format bytes. To accomplish this, the PLA determines at which time it is necessary to switch its own clock from one rate to the other. This function is done by the circuit illustrated in the figure. The line "GATE channel clock" is a line from the PLA which, when active, signifies that the PLA should be clocked at the channel rate.